1. Field of Invention
The present invention relates to a device of address space and the operation method on the device. More particularly, the present invention relates to a device for extending the address space by inserting a waiting state and the operation method on the device.
2. Description of Related Art
Currently, the technology on computer information science has been greatly developed. Various information storage cartridges have been accordingly developed, such as tape cartridge, disk cartridge, optical disc cartridge, memory cartridge, read-only memory cartridge, and so on. Various types of information can be stored in those cartridges, such as information, program, voice, or music. The conventional bus used between the external memory cartridge and the micro-controller has two types, including parallel bus and serial bus.
Referring to FIG. 5, it is a circuit block diagram, schematically illustrating an interface device using parallel bus. In FIG. 5, the device is a micro-controller 510, which is coupled to the external memory 150 through the parallel bus 540. Wherein, the micro-controller 510 includes a central processing unit (CPU) 512 and a read-only memory (ROM) 514. When the address of the information or the program to be executed by the CPU 512 is located at the external memory 150, the CPU 512 accesses the external memory 150 through the parallel bus 540. The interface of communication path between the micro-controller 510 and the external memory 150 is the parallel bus 540, so that the broadband request is necessary for the micro-controller 510 to access the information or the program from the external memory 150. However, the parallel interface has the disadvantage that the number of connection pins of the micro-controller 510 should be sufficient large for satisfying the broadband request, and it results in the increase of fabrication cost.
Referring to FIG. 6, it is a circuit block diagram, schematically illustrating a conventional serial address interface device having decoder. The interface device is a micro-controller 610, which is coupled to the external memory 150 through the serial bus 640. Wherein, the information or program to be executed by the CPU 512 is located at the external memory 150, the serial bus 640 is used to access the external memory 150. When the serial bus 640 is smaller than the bus of the ROM 514, all of the information or the program, stored in the external memory 150, are treated as the information during accessing stage. After the program, which has been treated as an information, is accessed to the micro-controller 610, it needs the decoder 516 to decode it by a script language, so as to recover the original program. Even though the serial address interface device of FIG. 6 can improve the parallel address interface device of FIG. 5 about reducing the fabrication cost, the serial address interface device of FIG. 6 still has several disadvantages as follows: (1) The conventional serial address interface device needs the script language to decode the accessed information, and it takes a lot of time to pre-build up the needing script language. (2) The conventional serial address interface device occupies at least a portion of memory resource of ROM/RAM during the decoding process.